1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer wiring structure using a low-dielectric-constant interlayer insulation film, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Materials having a relative dielectric constant of 3 or lower have recently been used for low dielectric constant interlayer insulation films in order to increase the operation speed of an LSI. The Young's modulus of such a low dielectric constant insulation film is generally about 10 GPa or lower. The coefficient of linear expansion of Cu used as wiring materials is as large as about 16 ppm. However, when a Cu wiring layer is formed, a barrier metal layer comprising refractory metal such as Ta and Ti and a compound thereof, is formed between the Cu wiring layer and an interlayer insulation film. The coefficient of linear expansion of barrier metal is not larger than 10 ppm and smaller than that of Cu. Thus, a great thermal stress is exerted on the barrier metal layer due to a difference in coefficient of linear expansion between barrier metal and Cu wiring layer during a high-temperature process such as annealing and sintering.
If the Young's modulus of the low-dielectric-constant insulation film is sufficiently large, the stress applied to the barrier metal layer can be decreased by suppressing the thermal expansion of Cu. However, the Young's modulus of the low dielectric constant insulation film is about 10 GPa or lower, as described above. Therefore, the thermal stress applied to the barrier metal layer becomes great and causes a crack to the low dielectric constant insulation film.
It is around a via hole that such a crack is most likely to occur. Referring to FIGS. 1A to 1C, a problem of the crack in the wiring structure of a prior art semiconductor device will be described.
As shown in FIG. 1A, an insulation film 1 having a laminated structure of a low dielectric constant insulation film 1a and a high fracture strength cap insulation film 1b is formed on a semiconductor substrate 24 and a lower wiring layer 2 is buried in the insulation film 1 with a barrier metal layer 9 interposed therebetween. An etching stopper insulation film 3, a low dielectric constant insulation film 4, and a high fracture strength cap insulation film 5 are formed in sequence. As shown in FIG. 1B, a via hole 6 connected to the lower wiring layer 2 and a wiring groove 7 are formed in the insulation films 3, 4 and 5 by RIE (reactive ion etching). Then, the surface of the low dielectric constant insulation film 4 is damaged by the RIE to form a low fracture strength damaged layer 8.
After that, as shown in FIG. 1C, barrier metal is deposited in the via hole 6 and on the entire surface of the wiring groove 7 by sputtering. The barrier metal layer 9 formed on the sidewalls of the via hole 6 is thinner than that formed on the sidewalls and bottom of the wiring groove 7 and the bottom of the via hole 6. Then, conductive materials 10 such as Cu are deposited and the resultant structure is annealed at high temperature. During the high temperature annealing, a tensile stress is exerted on the barrier metal layer 9 due to a difference in coefficient of linear expansion between them.
Since, in particular, the barrier metal layer 9 formed on the sidewalls of the via hole 6 is thin, it is likely to be cracked by the tensile stress. The fracture strength of the damaged layer 8 that is formed in contact with the barrier metal layer 9 is low and thus the crack caused in the barrier metal layer 9 might come into the low dielectric constant insulation film 4 through the damaged layer 8. Consequently, the conductive materials 10 such as Cu, which are compressed at high temperature, are protruded from the crack and a short circuit will occur.